DIGITAL CLOCK USING VERILOG

OBJECTIVE

Our objective is to design a FPGA based digital clock. We are using the FPGA other than the micro controller because we can connect many devices which can be monitored and the FPGA can be used as a controller or a processor.The design has been described using Verilog and implemented in hardware using FPGA (Field Programmable Gate Array). Our system was designed to control the door, window, garage door, fire alarm, luminosity, and temperature. It is not designed to control any other device. The academic goal of this project is to develop specific skills in designing, programming, testing and debugging.

INTRODUCTION

A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands.

Digital clocks are often associated with electronic drives, but the "digital" description refers only to the display, not to the drive mechanism. (Both analog and digital clocks can be driven either mechanically or electronically, but "clockwork" mechanisms with digital displays are rare.) The biggest digital clock is the Lichtzelt Pegel ("Light Time Level") on the television tower Rheinturm Düsseldorf, Germany.

Digital clocks typically use the 50 or 60 hertz oscillation of AC power or a 32,768 hertz crystal oscillator as in a quartz clock to keep time. Most digital clocks display the hour of the day in 24-hour format; in the United States and a few other countries, a more commonly used hour sequence option is 12-hour format[citation needed] (with some indication of AM or PM). Some timepieces, such as many digital watches, can be switched between 12-hour and 24-hour modes. Emulations of analog-style faces often use an LCD screen, and these are also sometimes described as "digital".

LITERATURE REVIEW

 This will discuss about the research and reviews on works of other researchers that have done to this related project. This chapter contained six subtopic which include the review on Cadence Design of clock/calendar using 240*8 bit RAM using Verilog HDL. This paper is from K.L University, Guntur by K.R.N. Karthik et.al. Second subtopic is about FPGA Based Digital Electronic Education Clock-Calendar Design. This paper is from Turgut Ozal University, Turkey by Vedat Kiray. Third subtopic is about Design of Calendar Clock Based on DS12C887 Chip. This paper is from Nanjing University of Information Science and Technology by Xiao Chen. Forth subtopic is about Design and Construction of a Four-hourly Digital Alarm Clock. This paper is from Pelagia research Library by Ochala, I, Momoh, O. Y, and Gbaorun, F. The fifth subtopic is about Real Time Calendar Applications in Actel Fusion Devices. This paper is from the Actel Corporation. At the end of this chapter, it is briefly explain on the difference between the proposed 6 2.1 Cadence Design of clock/calendar using 240*8 bit RAM using Verilog HDL.. In this paper, it is about Cadence design clock calendar using 2048 bit RAM using Verilog HDL. This design is organized as 256 words by 8 bits with address and data are transferred serially via the two-line bidirectional I2C-bus . This module is using the Verilog language with Xilinx and Cadence 90nm in Linux environment. From the above block diagram, it consists of six modules which are counter, alarm register, sound alarm, update register, RAM and I2C. It is also included the SDA and SCL line which consist of nine clock pulse of 8 bit data. This module has a standard clock of 100 kHz. As a conclusion, this paper is about designing a clock calendar using Cadence with Verilog HDL. It can be used in various digital circuitry at the same time reduces the design time of the digital circuits. Practically, it designs its layout using Cadence 90nm technology and implements it in Verilog using Xilinx. 7 2.2 FPGA Based Digital Electronic Education, Clock Calendar Design. This paper is a case study based on the Project Based Learning for the Electronics and Computer Engineering students to design a circuit and implemented it in the FPGA. It involved with building a block from a circuit and putting the block together to get new blocks. The designed is divided into three sub block as counting, setting and display. In the counting block, it taught the students to design a comparator, convert the circuit into counter and obtain the block to have a counter for seconds, minutes, hour, day, month and year. It then used the simulation results to evaluate the performance.The difference between the clock and calendar is from the signal that was sent to calendar block as input pulse . 8 In the setting block, this is where the students will have to add something for the design according to the other blocks. This section is to help the students understand the function of the block better. It shows steps to set for the block such as using the AND gate, multiplexer, counter and decoder to be add in their design. The last task given to the student is to solve the up counting problem where it causes difficulty in usage and waste time. The last sub block is the display block. This is the most difficult part for the student as to display the results in a flash with intervals of a second for indicating the selected unit. It used many of multiplexer in the designed thus make it more complex. This part is to analyze the results on the board and understand if the clock calendar is at normal working condition. As for conclusion of this paper, it contains the information to study the graphic design of clock calendar system. It teaches from the basic of what circuits are involved and steps in designing a clock calendar system.This graphic design can be redesigned again using HDL codes.

VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communicationtechnologies were being developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in large scale integration technologies and system design applications. With the advent of very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in high-performance computing, controls, telecommunications, image and video processing, and consumer electronics has been rising at a very fast pace.

The current cutting-edge technologies such as high resolution and low bit-rate video and cellular communications provide the end-users a marvelous amount of applications, processing power and portability. This trend is expected to grow rapidly, with very important implications on VLSI design and systems design.

VLSI  DESIGN FLOW:

The VLSI IC circuits design flow is shown in the figure below. The various levels of design are numbered and the blocks show processes in the design flow.

Specifications comes first, they describe abstractly, the functionality, interface, and the architecture of the digital IC circuit to be designed.

Behavioral description is then created to analyze the design in terms of functionality, performance, compliance to given standards, and other specifications.

RTL description is done using HDLs. This RTL description is simulated to test functionality. From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic synthesis tools. A gatelevel netlist is a description of the circuit in terms of gates and connections between them, which are made in such a way that they meet the timing, power and area specifications.

Finally, a physical layout is made, which will be verified and then sent to fabrication.

VerilogHDL:

In the semiconductor and electronic design industry, Verilogisahardwaredescriptionlanguage(HDL)used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register- transfer level of abstraction. It is also used in the verificationofanalogandmixed-signalcircuits.

Hardware description languages such as Verilogdiffer from software programming languages because they includewaysofdescribingthepropagationoftimeand signal dependencies (sensitivity). There are two assignmentoperators,ablockingassignment(=),anda non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state- machine update without needing to declare and use temporary storage variables. Since these concepts are part of Verilog's language semantics, designers could quickly write descriptions of large circuits in a relatively compact and concise form. At the time of Verilog's introduction (1984), Verilog represented a tremendous productivity improvement for circuit designers who were already using graphical schematic capture software and specially written software programstodocumentandsimulateelectroniccircuits.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports. Internally,amodulecancontainanycombinationofthe following: net/variable declarations (wire, reg,integer,etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed inside a begin/end blockandexecutedinsequentialorderwithintheblock. However, the blocks themselves are executed concurrently,makingVerilogadataflowlanguage.

During the development cycle the description has to become more and more precise until it is actually possible to manufacture the product. The (automatic) transformationofalessdetaileddescriptionintoamore elaborated one is called synthesis. Existing synthesis tools are capable of mapping specific constructs of hardwaredescriptionlanguagesdirectlytothestandard components of integrated circuits. This way, a formal model of the hardware system can be used from the early design studies to the final net list. Software supportisavailableforthenecessaryrefinementsteps.

Existing  Systems

Most commercially available home automation systems are all-in-one solutions which require that all controllable appliances are from the same company,or must be approved as compatible with said company‟s system.Moreoverthesesystemsnormallycomewitha proprietary, dedicated device which acts as the control centre. To control the system from multiple locations, additional control devices must be purchased.

These complex systems usually need to be integrated when the building is constructed and must be planned inadvance.Theyarealsodifficulttoupgradeorreplace once installed. The overall investment adds up considerablyandisfinanciallyinfeasibleinmostcases. Thesedrawbackshinderthepopularityofsuchsystems.

Proposed Systems

Theobjectiveoftheproposedsystemistoofferalow- cost solution for a home automation system that overcomes the above drawbacks. The system provides basic control of appliances at a fraction of the cost of commercially availablesystems.

The concept of a proprietary control device is done away with sensors such as LDR ,PIR sensor ,smoke sensor which gives input to the module, such as a mobile phone or laptop. There is no need for a specialized server system as a typical desktop PC can actastheserver.Nowadaysmostusersalreadyownthe requisites such as a mobile phone and a desktop PC; hencethecostofthesystemisconsiderablyreduced.

BLOCK DIAGRAM:

 

rk resistance of 2 Mega

Ohm

FPGA DESIGN  FLOW:

 Xilinx ISE Brief procedure:

ISE 13.2i Quick Start procedure

The ISE 13.2i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the basic design process using ISE 13.2i. After you have completed the tutorial, you will have an understanding of how to create, verify, and implement a design.Note: This tutorial is designed for ISE 13.2i on Windows.

This procedure contains the following sections:

• “Getting Started”

• “Create a New Project”

• “Create an HDL Source”

• “Design Simulation”

• “Create Timing Constraints”

• “Implement Design and Verify Constraints”

• “Reimplement Design and Verify Pin Locations”

• “Download Design to the Spartan™-3 Demo Board”

For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

Getting Started

Software Requirements:

To use this tutorial, you must install the following software:

• ISE 13.2i

Hardware Requirements:

To use this tutorial, you must have the following hardware:

• Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board

Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE  → Project Navigator

Note: Your start-up path is set during the installation process and may differ from the one above.

Accessing Help

At any time during the tutorial, you can access online help for additional information

about the ISE software and related tools.

To open Help, do either of the following:

• Press F1 to view Help for the specific tool or function that you have selected or

Highlighted.

• Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

ISE Help Topics

Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3e Startup Kit demo board.

To create a new project:

1. Select File >New Project... The New Project Wizard appears.

2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically.

4. Verify that HDL is selected from the Top-Level Source Type list.

5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:

♦ Product Category: All

♦ Family: Spartan3E

♦ Device: XC3S500E

♦ Package: FG320

♦ Speed Grade: -4

♦ Top-Level Module Type: HDL

♦ Synthesis Tool: XST (VHDL/Verilog)

♦ Simulator: ISE Simulator (VHDL/Verilog)

♦ Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields.

When the table is complete, your project properties will look like the following:

Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.

Create a Verilog HDL Source

In this section, I will create the a example top-level Verilog HDL file

Creating a Verilog Source

Create the top-level Verilog source file as follows:

1. Click New Source in the New Project dialog box.

2. Select Verilog Module as the source type in the New Source dialog box.

3. Type in the file name counter.

4. Verify that the Add to Project checkbox is selected.

5. Click Next.

6. Declare the ports for the counter design by filling in the port information as shown below: Define Module

7. Click Next, then Finish in the New Source Information dialog box to complete the new source file template.

8. Click Next, then Next, then Finish.

The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below:

New Project in ISE

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter.

Use a simple counter code example from the ISE Language Templates and customize it for the counter design.

1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.

2. Open the Language Templates by selecting Edit → Language Templates…

Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible.

3. Using the “+” symbol, browse to the following code example:

Verilog → Synthesis Constructs → Coding Examples → Counter → Binary →

Up/Down Counters → Simple Counter

4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in File toolbar button. This step copies the template into the counter source file.

5. Close the Language Templates.

Final Editing of the Verilog Source

1. To declare and initialize the register that stores the counter value, modify the

declaration statement in the first line of the template as follows:

replace: reg [<upper>:0] <reg_name>;

with: reg [3:0] count_int = 0;

2. Customize the template for the counter design by replacing the port and signal name

placeholders with the actual ones as follows:

♦ replace all occurrences of <clock> with CLOCK

♦ replace all occurrences of <up_down> with DIRECTION

♦ replace all occurrences of <reg_name> with count_int

3. Add the following line just above the endmodule statement to assign the register value to the output port:

assign COUNT_OUT = count_int;

4. Save the file by selecting File → Save.

When you are finished, the code for the counter will look like the following:

module counter(CLOCK, DIRECTION, COUNT_OUT);

input CLOCK;

input DIRECTION;

output [3:0] COUNT_OUT;

reg [3:0] count_int = 0;

always @(posedge CLOCK)

if (DIRECTION)

count_int <= count_int + 1;

else

count_int <= count_int - 1;

assign COUNT_OUT = count_int;

endmodule

You have now created the Verilog source for the tutorial project.

Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors and typos.

1. Verify that Synthesis/Implementation is selected from the drop-down list in the

Sources window.

2. Select the counter design source in the Sources window to display the related

processes in the Processes window.

3. Click the “+” next to the Synthesize-XST process to expand the process group.

4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.

5. Close the HDL file.

Design Simulation

Verifying Functionality using Behavioral Simulation

Create a test bench waveform containing input stimulus you can use to verify the

functionality of the counter module. The test bench waveform is a graphical view of a test bench.

Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window.

2. Create a new test bench source by selecting Project → New Source.

3. In the New Source Wizard, select Verilog test fixture as the source type, and type counter_tbw in the File Name field.

4. Click Next.

5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next.

6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish.

7. Save the waveform.

8. Close the test bench waveform.

HARDWARE  IMPLEMENTATION ON FPGA

OVERVIEW OF FPGA

 

Before the advent of programmable logic, custom logic

circuits were built at the board level using standard components, or at the gate level in expensive application-specific (custom) integrated circuits. FPGAs are a distinct from SPLDs and CPLDs

and typically offer the highest logic capacity. The FPGA is an integrated circuit that contains

many 64 to over 10,000 identical logic cells and an even greater number of flip-flops that can be viewed as standard components. Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a matrix of wires and

programmable switches. A user's design is implemented by specifying the simple logic function

for each cell and selectively closing the switches in the interconnect matrix. The arrays of logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex designs

are     created    by    combining   these    basic    blocks    to     create    the     desired         circuit.

         

Basic Structure of an FPGA

FPGA architecture consists of three types of configurable elements - a perimeter

of input/output blocks (IOBs), a core array of configurable logic blocks (CLBs), and resources

for interconnection as shown in fig .The IOBs provide a programmable interface between the internal array of logic blocks (CLBs) and the device's external package pins. CLBs perform user-specified logic functions, and the interconnect resources carry signals among the block.

With rise in sophistication of digital VSLI designs, chips are being fabricated with

millions of transistors involving large RTL codes. This leads to numerous problems in verification of the design because of the dramatic increase in the simulation run time. Therefore,

software verification of large ASICs and system-on-chip are not preferred. Simulation assisted

by special hardware and tools are gathering wide spread acceptance. The latest generation of FPGAs offers compelling platforms for hardware acceleration of computationally intensive software algorithms.

Field Programmable means that the FPGA's function is defined by a user's program

rather than by the manufacturer of the device. A typical integrated circuit performs a particular function defined at the time of manufacture. In contrast, the FPGA's function is defined by a

program written by someone other than the device manufacturer. Depending on the particular

device, the program is either 'burned' in permanently or semi-permanently as part of a board assembly process, or is loaded from an external memory each time the device is powered up. This user programmability gives the user access to complex integrated designs without the

high engineering costs associated with application specific integrated circuits.

Advantages to designing with an FPGA (instead of an ASIC or ASSP) include:

  Rapid prototyping

  Shorter time to market

  The ability to re-program in the field for debugging

  Lower NRE costs

  Long product life cycle to mitigate obsolescence risk

           

DIGITAL CLOCK

The block diagram of Digital Clock as shown above. It consists of a counter, comparator, multiplexer and decoder. In the clock calendar, counter performs the clock count with constant frequency/time period. The time period is defined by the clock generator that employed inside the counter. The clock generator generates the pulse of signal with rise and fall time transitions with described time interval. The counter can be defined to count the rise time or fall time transition of the clock pulse. For every rice/fall time transition the counter increases one with the present value. In this proposed design the counter is defined to count the rise time transition i.e., for every change of clock signal from logic 0 to logic 1 the counter increases the value by one, which helps to fix the second count of the circuit. Each second increment in the digital calendar is defined by increasing the count. The time delays between the seconds are defined by the time period of the clock signal. In this way the counter increases the count by one for every rise edge of clock pulse. When the count value in second reaches the value 60, the second value has been assigned back to 0 with the increment in minutes. Again the seconds counted from beginning to maximum value and then the count will be fixed with initial value by increasing the minutes by one from the present state.

Similarly to seconds, the minutes value has been increased with the some constant time delay that described by 60 set of seconds delay. When minute reaches to the maximum value 60 then the minute value will be set into initial value 0 by increasing one value in hour. Again the minutes counted from beginning to maximum value and then the count will be fixed with initial value by increasing the hour by one from the present state. Then for each count of maximum minute one hour will be increased by assigning minutes to 0 back. When hour reached to maximum value 24 day will be incremented. Days get incremented by one from the previous value every time the hour reaches to 24 and the hour will be assigned by 0 that starts count from beginning with seconds, and minutes.

In the digital calendar increment of day must be defined carefully since the months are incorporated different number of days with it. When the days are reaching to the maximum number in the month then the day has to be initiated by 0 with the increment in a month. Month increases whenever the day’s reaches to the maximum number defined for the particular month. The total delay between the months is defined by the delay of seconds/minutes/hours/days. When the months are reaching to the maximum number 12 then the month will be initiated to 0 with the increment in a year. Year increases whenever the months reach to the maximum number defined for year (12). The total delay between the years is defined by the delay of seconds/ minutes/ hours/ days/ months.

The logic multiplexer present in the digital clock calendar selects the count part seconds/ minutes/ hours/ days/ months/ years that to be incremented at the rise edge of clock pulse. The selection line defines which line has to be incremented by the counter for the response of rise time transition of clock signal.

Comparator present in the digital calendar identifies the maximum allowable integer value for seconds/ minutes/ hours/ days/ months/ years. Based on the comparison result from the comparator the digital counter counts are initiated to 0 with the increment of next higher order parameter.

The digital clock calendar counts seconds/ minutes/ hours/ days/ months/ years for the response of rise edge transition of clock signal. The outputs generated by the digital clock calendar sent to the seven segment display through the decoder. The decoder decodes the decimal input into binary code and then load as input to the seven segment display. The display shows the seconds/minutes/hours/days/months /years that obtained from the clock calendar.

The logic blocks and logics are implemented using hardware description language and simulated to verify the logic output. The simulation results are described in the next section that demonstrates the logic implementation of Digital clock calendar.

CODE

module Digital_Clock(

    Clk_1sec,  //Clock with 1 Hz frequency

    reset,     //active high reset

    seconds,

    minutes,

    hours);

//What are the Inputs?

    input Clk_1sec; 

    input reset;

//What are the Outputs?

    output [5:0] seconds;

    output [5:0] minutes;

    output [4:0] hours;

//Internal variables.

    reg [5:0] seconds;

    reg [5:0] minutes;

    reg [4:0] hours;

   //Execute the always blocks when the Clock or reset inputs are

    //changing from 0 to 1(positive edge of the signal)

    always @(posedge(Clk_1sec) or posedge(reset))

    begin

        if(reset == 1'b1) begin  //check for active high reset.

            //reset the time.

            seconds = 0;

            minutes = 0;

            hours = 0;  end

        else if(Clk_1sec == 1'b1) begin  //at the beginning of each second

            seconds = seconds + 1; //increment sec

            if(seconds == 60) begin //check for max value of sec

                seconds = 0;  //reset seconds

                minutes = minutes + 1; //increment minutes

                if(minutes == 60) begin //check for max value of min

                    minutes = 0;  //reset minutes

                    hours = hours + 1;  //increment hours

                   if(hours ==  24) begin  //check for max value of hours

                        hours = 0; //reset hours

                    end

                end

            end    

        end

    end    

endmodule

Testbench for Digital Clock:

module tb_clock;

    // Inputs

    reg Clk_1sec;

    reg reset;

    // Outputs

    wire [5:0] seconds;

    wire [5:0] minutes;

    wire [4:0] hours;

    // Instantiate the Unit Under Test (UUT)

    Digital_Clock uut (

        .Clk_1sec(Clk_1sec),

        .reset(reset),

        .seconds(seconds),

        .minutes(minutes),

        .hours(hours)

    );

   

    //Generating the Clock with `1 Hz frequency

    initial Clk_1sec = 0;

    always #50000000 Clk_1sec = ~Clk_1sec;  //Every 0.5 sec toggle the clock.

    initial begin

        reset = 1;

        // Wait 100 ns for global reset to finish

        #100;

        reset = 0; 

    end

     

endmodule

RESULT

RTL SCHEMATIC:

SIMULATION:

The code was simulated using Xilinx ISE 13.1. The waveform is long, and it's not possible to post the whole waveform here. I have shown two relevant sections in the waveform.

CONCLUSION

In this paper, the high performance digital clock design is proposed with reduced core area. The block diagram of clock is designed with the combination of comparator, counter, multiplexer and decoder. The simple blocks incorporated with the clock calendar reduced the area of the design appropriately. The performance of the calendar is improves with highly adoptable clocking technique. The blocks are implemented using HDL and verified in the modelsim simulator. The HDL program is also synthesized to obtain the logic blocks and sub-blocks of digital clock. The demonstration of digital clock is performed with the Spartan®-6 FPGA SP605 Evaluation Kit.

In our project we have integrated three sensors with FPGA i.e., LDR, PIR sensor and LM35.LDR controls the lighting of the compound. IR sensors operate the opening of garage door. It is also responsible for monitoring the interior lighting and fan regulation. Temperature senor (LM35) manages the temperature control of the air condition.There have been many assumptions all through, but efforts have been put in to make it as practical as possible. This is a low cost and effective device. This method is very easy to adapt and implement and can easily be embedded to another device.

We used Verilog HDL to implement the code part has really helped since it not only combines the hardware and software part, it also provides informative graphs and waveforms which are helpful in understanding the real concept of the project. Xilinx also has proved to be the most robust and learnable tool for simulation and a great integrated development environment.

FUTURE SCOPE

A digital clock built into an oven

A digital light clock that can determine room temperature

Because digital clocks can be very small and inexpensive devices that enhance the popularity of product designs, they are often incorporated into all kinds of devices such as cars, radios, televisions, microwave ovens, standard ovens, computers and cell phones. Sometimes their usefulness is disputed: a common complaint is that when time has to be set to Daylight Saving Time, many household clocks have to be readjusted. The incorporation of automatic synchronization by a radio time signal is reducing this problem (see Radio clock).

REFERENCES

 [1] Sell. A, Walden, P, “Mobile Digital Calendars: An Interview Study”, System Sciences, 2006. IEEE HICSS '06, pp. 23b

[2] I-Long Lin, Han-Chieh Chao, Shih-Hao Peng, “Research of Digital Evidence Forensics Standard Operating Procedure with Comparison and Analysis Based on Smart Phone”, BWCCA’2011, IEEE’11, pp.386-391.

[3] Wei-Ming Lin, Chao-Chyun Chen, Shen-Iuan Liu, “An all-digital clock generator for dynamic frequency scaling”, VLSI-DAT, IEEE’2009, pp.251-254.

[4] Moo-Young Kim, Shin, Dongsuk, Hyunsoo Chae, Chulwoo Kim, “A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time”, VLSI systems, IEEE’2009, pp.1461-1469.

[5] Gaughan, W, Butka Brian, “Using an FPGA digital clock manager to generate sub-nanosecond phase shifts for lidar applications”, Programmable Logic Conference (SPL), 2010 VI Southern, IEEE 2010, pp.163-166.

[6] Batarseh, M.G, Orlando, FL Al-Hoor, W.Huang, L.Iannello, “Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique” PESC 2008. IEEE, pp.3036-3042.

[7] Kilada, E, Dessouky.M, Elhennawy. A,“FPGA implementation of a fully digital CDR for plesiochronous clocking systems”, Microelectronics, 2007. ICM 2007, pp.299 – 302.

[8] Batarseh, M.G, Al-Hoor, W. Huang, L.Iannello, “Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique”, Power Electronics, IEEE Transactions, Nov.2009, pp. 2649 – 2660.

[9] Linfeng Shang, Kezhu Song, Ping Cao, Cheng Li, “A Prototype Clock System for LHAASO WCDA”, Nuclear Science, IEEE Transactions, Oct 2013, pp. 3537 – 3543.